Certain signal processing applications use multipliers to perform mathematic operations such as multiplication. A multiplier multiplies one or more input signals to produce a product signal that is proportional to the input signals.
FIG. 1 shows a conventional multiplier. Conventional multiplier 100 has Transistors M1 and M2 to receive input signals Vs1 and Vs2 to produce currents Ix and Iy. Transistors M3 and M5 pass Ix to nodes 101 and 102. Transistors M4 and M6 pass Iy to nodes 101 and 102. At node 101, current Ia equals the sum of a portion of Ix and a portion of Iy. At node 102, current Ib equals the sum of another portion of Ix and another portion of Iy. A weighting voltage Vw is applied to the gates of transistors M4 and M5. Ia and Ib are the product of Vs1 and Vs2 and Vw.
In multiplier 100, the sum of Ia and Ib equals the sum of Ix and Iy because all of Ix and Iy flow to nodes 101 and 102. In some applications, the full amount of Ix and Iy flowing to node 101 and 102 is too great. The output current could overload a circuit connected to the output of the multiplier.
For these and other reasons stated below, and which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for an improved multiplier.